1. Field of the Disclosure
The present disclosure generally relates to image sensor technology, and more particularly, to a CMOS image sensor, a pixel unit and a method for controlling the pixel unit.
2. Discussion of the Background Art
Image sensors are important parts of digital cameras. According to components they have, the image sensors can be divided into two types: Charge Coupled Device (CCD) image sensors and Complementary Metal-Oxide Semiconductor (CMOS) image sensors. CMOS image sensors have been widely used in different fields, attributed to their outstanding performance such as low power consumption, low cost and good compatibility with standard production line.
According to exposure modes, CMOS sensors can be divided into two types: line-by-line exposure CMOS image sensors and global exposure CMOS image sensors. Generally, a pixel unit of the CMOS image sensor includes a photodiode and a plurality of transistors. According to a number of the transistors they have, the pixel units of the CMOS image sensor can be classified into 3-transistor (3T) type, 4-transistor (4T) type and 5-transistor (5T) type.
According to an American patent with a publication number of U.S. Pat. No. 6,566,697, entitled “Pinned photodiode five transistor pixel”, a pixel unit of a 5T-type global exposure CMOS image sensor is disclosed. A structure diagram of the pixel unit is illustrated in FIG. 1. Referring to FIG. 1, the pixel unit of the 5T-type global exposure CMOS image sensor includes one photodiode PPD and five NMOS transistors including a reset transistor M11, an amplifier transistor M12, a selection transistor M13, a transmission transistor M14 and a global reset transistor M15.
A source of the reset transistor M11 serves as a storage node FD (namely, a floating diffusion area) for storing signals temporarily. A drain of the reset transistor M11, a drain of the amplifier transistor M12 and a drain of the global transistor M15 are connected to a first power line Vdd. A positive electrode of the photodiode is connected to a second power line Vss. A voltage provided by the second power line Vss is lower than a voltage provided by the first power line Vdd. Generally, the first power line Vdd provides a power voltage for supplying the CMOS image sensor, and the second power line Vss provides a ground voltage. A source of the selection transistor M13 is adapted for connecting to a column selection line Bitline.
The reset transistor M11 is adapted for resetting the storage node FD before the pixel unit is exposed, so as to raise the storage node FD from a low potential to a predetermined high potential. The global reset transistor M15 is adapted for resetting the photodiode PPD before the pixel unit is exposed. The photodiode PPD is adapted for performing photoelectric conversion and converting optical signals to electrical signals when the pixel unit is exposed. The transmission transistor M14 is adapted for transmitting the electrical signal obtained by the photodiode PPD to the storage node FD. The amplifier transistor M12 adapted for amplifying the electrical signal received from the storage node FD. The selection transistor M13 is adapted for transmitting the amplified electrical signal to the column selection line Bitline.
FIG. 2 illustrates an operation timing diagram of the pixel unit shown in FIG. 1, wherein RST stands for a reset control signal received by a gate of the reset transistor M11, SEL stands for a row selection signal received by a gate of the selection transistor M13, TX stands for a transmission signal received by a gate of the transmission transistor M14, and rst stands for a global reset signal received by a gate of the global reset transistor M15. A working process of the pixel unit shown in FIG. 1 will be described below in conjunction with FIG. 2.
Referring to FIG. 2, at a beginning of an operation period, the reset control signal RST is a high level signal, such that the reset transistor M11 is turned on to reset the storage node FD and raise the storage node FD to a high potential.
At the time of t20, the global reset signal rst is switched from a low level signal to a high level signal, such that the global reset transistor M15 is turned on and the photodiode PPD is reset.
At the time of t21, the global reset signal rst is switched from a high level signal to a low level signal, such that the global reset transistor M15 is turned off, and the photodiode PPD performs photoelectric conversion, and converts optical signals to electrical signals.
At the time of t22, the photodiode PPD finishes photoelectric conversion and the transmission signal TX is switched from a low level signal to a high level signal; such that the transmission transistor M14 is turn on to transmit the electrical signals obtained by the photodiode PPD to the storage node FD. At this time, the signal stored in the storage node FD is an exposure signal Vsig. A time period between t21 and t22 is an exposure period of the photodiode PPD. In the exposure period, the reset control signal RST is switched from a high level signal to a low level signal.
After a period of time when the transmission transistor M14 is turned off, the row selection signal SEL is switched from a low level signal to a high level signal, such that the selection transistor M13 is turned on. At the time of t23, the exposure signal Vsig is read out to the column selection line Bitline.
After the exposure signal Vsig is read out, the reset transistor M11 resets the storage node FD again. After the reset operation, the signal stored in the storage node FD is a reset signal Vrst. At the time of t24, the reset signal Vrst is read out to the column selection line Bitline. A difference between the reset signal Vrst and the exposure signal Vsig is an image signal generated by the pixel unit.
At the time of t25, the reset control signal RST is switched from a low level signal to a high level signal, and the pixel unit starts a new operation period.
After the image signal obtained by the pixel unit shown in FIG. 1 is transmitted through a series of CMOS circuits, reset noises are generated by control pulse signals of the circuits. In order to reduce impacts of the reset noises, a Correlated Double Sampling (CDS) technology is usually employed.
According to an American patent application with a publication number of US20090256060A1, entitled “Pixel array with global shutter”, a pixel unit of an 8T type global exposure CMOS image sensor is disclosed. A structure diagram of the pixel unit is illustrated in FIG. 3. Compared with the pixel unit shown in FIG. 1, the pixel unit shown in FIG. 3 reduces the global reset transistor, but adds a first sampling capacitance C12, a second sampling capacitance C22, a first switch transistor M21, a second switch transistor M22, a discharge transistor M23 and an amplifier transistor M24.
FIG. 4 illustrates an operation timing diagram of the pixel unit shown in FIG. 3, wherein SMP1 stands for a first control signal received by a gate of the first switch transistor M21, SMP2 stands for a second control signal received by a gate of the second switch transistor M22, and PC stands for a discharge signal obtained by a gate of the discharge transistor M23. A working process of the pixel unit shown in FIG. 3 will be described below in conjunction with FIG. 4.
Referring to FIG. 4, at a beginning of an operation period, the reset control signal RST is a high level signal, such that the reset transistor M11 is turned on to reset the storage node FD and raise the storage node FD to a high potential. That is, the storage node FD stores a reset signal Vrst.
At the time of t40, both the first control signal SMP1 and the second control signal SMP2 are switched from a low level signal to a high level signal, such that the first switch transistor M21 and the second switch transistor M22 are turned on, the reset signal Vrst is stored in the first sampling capacitance C21 and the second sampling capacitance C22, and both a voltage of the first sampling capacitance C21 and a voltage of the second sampling capacitance C22 are the same as a voltage of the reset signal Vrst.
At the time of t41, the second control signal SMP2 is switched from a high level signal to a low level signal, such that the second switch transistor M22 is turned off. In addition, before the time of t41, the reset control signal RST is switched from a high level signal to a low level signal, such that the reset transistor M11 is turned off.
At the time of t42, the transmission signal TX is switched from a low level signal to a high level signal, such that the transmission transistor M14 is turned on to transmit the electrical signals obtained by the photodiode PPD to the storage node FD. That is, the storage node FD stores an exposure signal Vsig.
At the time of t43, the discharge signal PC is switched from a low level signal to a high level signal, such that the discharge transistor M23 is turned on to reset the first sampling capacitance C21. After the reset operation, the amplifier transistor M12 stores the exposure signal Vsig in the first sampling capacitance C21, the first control signal SMP1 is switched from a high level signal to a low level signal, and the first switch transistor M21 is turned off.
At the time of t44, the reset control signal RST is switched from a low level signal to a high level signal, such that the reset transistor M11 is turn on, and the storage node FD is reset again.
At the time of t45, the row selection signal SEL is switched from a low level signal to a high level signal, such that the selection transistor M13 is turned on, and reset signal Vrst stored in the second sampling capacitance C22 is read out to the column selection line Bitline.
Then, the second control signal SMP2 is switched from a low level signal to a high level signal, such that the second switch transistor M22 is turned on. According to a charge-sharing effect, after the second switch transistor M22 is turn on, a voltage of the first sampling capacitance C21 is equal to a voltage of the second sampling capacitance C22. An electrical signal on the second sampling capacitance C22 is (Vrst-Vsig)/2.
After the second control signal SMP2 is switched from a high level signal to a low level signal, the electrical signal in the second sampling capacitance C22 is read out to the column selection line Bitline. At the time of t46, the row selection signal SEL is switched from a high level signal to a low level signal, and a process for reading the reset signal Vrst and the exposure signal Vsig is finished.
In the process for the pixel unit shown in FIG. 4 reading the reset signal Vrst and the exposure signal Vsig, the first sampling capacitance C21 and the second sampling capacitance C22 shares the exposure signal Vsig, which results in that the useful signal decays a half, Signal to Noise Ratio (SNR) of the image signal generated by the pixel unit is decreased, and the image generated by the CMOS image sensor has a poor quality.